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| fujitsu microelectronics data sheet copyright?2002-2008 fujitsu microelect ronics limited all rights reserved 2008.10 for the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc - 16lx mb90440g series mb90443g/f443g/v440g description the mb90440g series with full-can and flash rom is a line of general-purpose, fujitsu microelectronics 16-bit microcontrollers specially designed for automotive and industrial applications. its main features are three on board can interfaces (generic type) , which conform to v2.0 part a and part b, supporting very flexible message buffering. thus, more functions than a normal full can approach is available. while inheriting the at architecture of the f 2 mc * family, the instruction set for the f 2 mc-16lx cpu core incorpo- rates additional instructions for high-level languages, supports extended addressing modes, and contains en- hanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90440g series has as on-chip 32-bit accumulator, which enables processing of long-word data. the peripheral resources integrated in the mb90440g series include; an 8/10-bit a/d converter, uarts (sci) , i/o extended serial interface, 8/16-bit ppg timer, input/output timer (input capture (icu) , output compare (ocu) ) . * : f 2 mc is the abbreviation of fujitsu flexible microcontroller. ds07-13716-3e
mb90440g series 2 ds07-13716-3e features ? clock internal pll clock multiplication circuit base oscillation divided into tw o or multiplied by one to four minimum execution time : 62.5 ns (4 mhz os cillation, pll clock multiplication multiplier = 4, v cc = 5.0 v) 32 khz subsystem clock ? instruction set optimized for controller applications supported data types : bit, byte, word, and long-word types standard addressing modes : 23 types singed multiplication/division and extended ret1 instructions 32-bit accumulator enhancing high-precision operations ? enhanced high level language (c) and multi-tasking support instructions use of a system stack pointer symmetrical instruction set and barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed : 4 byte instruction queue ? enhanced interrupt function : 8 priority levels programmable and 34 causes ? automatic data transmission function independent of cpu operation extended intelligent i/ o service function (ei 2 os) ? internal rom size and type flash rom : 128 kbytes internal ram size : 6 kbyte and 14 kbyte (evaluation chip) ? flash rom supports automatic programming function, embedded algorithm writing command/erase command/erase suspend and resume command algorithms completion flag hardwire reset vector to show the fixed boot code sector can be erased by each sector sector protection by external programming voltage ? low-power consumption (stand-by) modes sleep mode (cpu operating clock stops) stop mode (main oscillation stops) cpu intermittent operation mode watch mode time-base timer mode ? general-purpose i/o ports : 81 ports ? timers watchdog timer : 1 channel 8/16-bit ppg timer : 8/16-bit 4 channels 16-bit reload timer : 2 channels (continued) mb90440g series ds07-13716-3e 3 (continued) ? 16-bit i/o timers 16-bit free-run timers : 1 channel 16-bit input capture : 8 channels 16-bit output compare : 4 channels ? extended i/o serial interfaces : 1 channel ? uart0 full-duplex, double-buffered (8 bit) can be used for clock synchronous and asynchronous transfer (with start/stop bit) ? uart1 (sci) full-duplex, double-buffered (8 bit) can be used for clock synchronous and asynchronous serial transfer (extended i/o serial) ? external interrupt inputs : 8 channels extended intelligent i/o service (ei 2 os) is started by external input and external interrupt generation module ? delayed interrupt generation module : interrupt request for task switching ? 8/10 bit a/d converter : 8 channels 8/10-bit resolution selectable can be started by external trigger input conversion time : 6.12 s ? full-can interface 3 channels conform to v2.0 part a and part b supports very flexible message buffering (mail-box and fifo buffering can be mixed) ? external bus interface : maximum 16 mbyte address space mb90440g series 4 ds07-13716-3e product lineup the following table provides a quick outlook of the mb90440g series (continued) part number mb90443g (under development) MB90F443G mb90v440g parameter cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 1/2 when pll stops) minimum instruction execution time : 62.5 ns (4 mhz osc. pll 4) rom size mask rom 128 kbytes flash memory 128 kbytes external ram size 6 kbytes 6 kbytes 14 kbytes operating *1 voltage range 5 v 10 % temperature range ? 40 c to + 105 c package qfp100 pga-256 voltage dedicated for emulator *2 ? no uart0 full duplex double buffer supports clock asynchronous/synchro nous (with start/stop bits) transfer baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 k/1 m/2 mbps (synchronous) at system clock = 16 mhz uart1 (sci) full duplex double buffer asynchronized (start/stop bits synchronized) and clk-synchronous communication baud rate : 601 bps to 250 kbps (asynchronous) 31.25 kbps to 2 mbps (synchronous) serial io transfer can be started from msb or lsb supports internal clock synchronized transfer and external clock synchronized transfer supports positive-edge and negative-edge clock synchronization baud rate : 31.25 k/62.5 k/125 k/500 k/1 m/2 mbps at system clock = 16 mhz 8/10 bit a/d converter 10-bit or 8-bit resolution 8 input channels conversion time : 6.12 s (per one channel) 16-bit reload timer (2 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function 16-bit free-run timer signals an interrupt during overflow supports timer clear during a match with output compare (channel 0) operation clock freq. : fsys/2 2 , fsys/2 4 , fsys/2 6 , fsys/2 8 (fsys = system clock freq.) 16-bit output compare (4 channels) signals an interrupt during a match with 16-bit free-run timer four 16-bit compare registers a pair of compare registers can be used to generate an output signal mb90440g series ds07-13716-3e 5 (continued) *1 : values with conditions such as the operating frequency (see section ? electrical characteristics?) . *2 : dip switch s2 when using emulation pad mb2145-507. the details are referred to hardware manual of mb2145-507. part number mb90443g (under development) MB90F443G mb90v440g parameter 16-bit input capture (8 channels) rising edge, falling edge or ri sing & falling edge sensitive four 16-bit capture registers signals an interrupt upon external event 8/16-bit programmable pulse generator (4 channels) supports 8-bit and 16-bit operation modes eight 8-bit reload counters eight 8-bit reload registers for l pulse width eight 8-bit reload registers for h pulse width a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins operation clock frequency. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = system clock frequency, fosc = oscillation clock frequency) can interface 3 channels : conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame supports prioritized 16 message buffers for data and id flexible configuration of acceptance filtering : full bit compare / full bit mask / two partial bit masks supports up to 1 mbps external interrupt (8 channels) can be programmed edge detection or level detection external bus interface the external access used selective 8-bit bus or 16-bit bus is available. (external bus mode) i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs and schmitt trigger inputs bit-wise programmable as input/output or peripheral signal 32 khz subclock sub-clock for low power operation flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block block protection with external programming voltage mb90440g series 6 ds07-13716-3e pin assignment (top view) (fpt-100p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl/wr p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sot0 p41/sck0 p42/sin0 p43/sin1 p44/sck1 v cc p45/sot1 p46/sot2 p47/sck2 c p50/sin2 p51/int4 p52/int5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 x0a x1a pa0/int3 rst p97/rx1 p96/tx1 p95/int2/rx0 p94/tx0 p93/rx2 p92/tx2 p91/int1 p90/int0 p87/tot1 p87/tin1 p85/out1 p84/out0 p83/ppg3 p82/ppg2 p81/ppg1 p80/ppg0 p77/out3/in7 p76/out2/in6 p75/in5 p74/in4 p73/in3 p72/in2 p71/in1 p70/in0 n.c. md2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p53/int6 p54/int7 p55/adtg av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p56/tin0 p57/tot0 md0 md1 mb90440g series ds07-13716-3e 7 pin description (continued) pin no. pin name circuit type function 82 83 x0 x1 a (oscillation) high speed oscillator input pins 80 79 x0a x1a a (oscillation) low speed oscillator input pins 77 rst b external reset request input 52 n.c. ? not connected 85 to 92 p00 to p07 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this func- tion is enabled when the external bus is enabled. 93 to 100 p10 to p17 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode. ad08 to ad15 i/o pins for 8 higher bits of the external address/data bus. this func- tion is enabled when the external bus is enabled. 1 to 8 p20 to p27 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode. a16 to a23 i/o pins of 8 bits for a16 to a23 ot the external address bus. this function is enabled when the external bus is enabled. 9 p30 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode. ale address latch enable output pin. this function is enabled when the external bus is enabled. 10 p31 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode. rd read strobe output pin for the data bus. this function is enabled when the external bus is enabled. 12 p32 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode or when the wr /wrl pin output is disabled. wrl write strobe output pin for the data bus. this function is enabled when the external bus is in enable mode and the wr /wrl pin out- put is enabled. wrl is used as a write-strobe output pin for 8 lower bits of the data bus in 16-bit access while wr is used as a write- strobe output pin for 8 bits of the data bus in 8-bit access. wr 13 p33 h general i/o port with programmable pullup. this function is en- abled in the single-chip mode or external bus 8-bit mode or when w rh pin output is disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the ex- ternal bus 16-bit mode is selected, and when the wrh output pin is enabled. mb90440g series 8 ds07-13716-3e (continued) pin no. pin name circuit type function 14 p34 h general i/o port with programmable pullup. this function is enabled in the single-chip mode or when hold function is disabled. hrq hold request input pin. this function is enabled when the external bus is in enable mode and the hold function is enabled. 15 p35 h general i/o port with programmable pullup. this function is enabled in the single-chip mode or when hold function is disabled. hak hold acknowledge output pin. this function is enabled when the ex- ternal bus is in enable mode and the hold function is enabled. 16 p36 h general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the external ready function is dis- abled. rdy ready input pin. this function is enabled when the external bus is in enable mode and the external ready function is enabled. 17 p37 h general i/o port with programmable pullup. this function is enabled in the single-chip mode or when clk output is disabled. clk clk output pin. this function is enabled when the external bus is in enable mode and clk output is enabled. 18 p40 g general i/o port. this function is enabled when serial data output of uart0 is disabled. sot0 serial data output pin for uart0. this function is enabled when uart0 enables serial data output. 19 p41 g general i/o port. this function is enabled when clock output of uart0 is disabled. sck0 serial clock i/o pin for uart0. this function is enabled when uart0 enables serial clock output. 20 p42 g general i/o port. this function is always enabled. sin0 serial data input pin for uart0. set the corresponding ddr regis- ter to input if this function is used. 21 p43 g general i/o port. this function is always enabled. sin1 serial data input pin for uart1. set the corresponding ddr regis- ter to input if this function is used. 22 p44 g general i/o port. this function is enabled when serial clock output of uart1 is disabled. sck1 serial clock i/o pin for uart1. this function is enabled when uart1 enables serial clock output. 24 p45 g general i/o port. this function is enabled when serial data output of uart1 is disabled. sot1 serial data output pin for uart1. this function is enabled when uart1 enables serial data output. mb90440g series ds07-13716-3e 9 (continued) pin no. pin name circuit type function 25 p46 g general i/o port. this function is enabled when the extended serial i/o interface disables serial data output. sot2 serial data output pin for the extended serial i/o interface. this function is enabled when the extended serial i/o interface enables serial data output. 26 p47 g general i/o port. this function is enabled when the extended serial i/o interface disables serial clock output. sck2 serial clock i/o pin for the extended serial i/o interface. this func- tion is enabled when the extended serial i/o interface enables seri- al clock output. 28 p50 d general i/o port. this function is always enabled. sin2 serial data input pin for the extended serial i/o interface. set the corresponidng ddr register to input if this function is used. 29 to 32 p51 to p54 d general i/o ports. this function is always enabled. int4 to int7 external interrupt request input pins for int4 to int7. set the cor- responding ddr register to input if this function is used. 33 p55 d general i/o port. this function is always enabled. adtg external trigger input pin for the 8/10-bit a/d converter. set the cor- responding ddr register to input if this function is used. 38 to 41 p60 to p63 e general i/o ports. the function is enabled when the analog input enable register specifies port. an0 to an3 analog input pins for the 8/10-bit a/d converter. this function is en- abled when the analog input enable register specifies a/d. 43 to 46 p64 to p67 e general i/o ports. the function is enabled when the analog input enable register specifies port. an4 to an7 analog input pins for the 8/10-bit a/d converter. this function is en- abled when the analog input enable register specifies a/d. 47 p56 d general i/o port. this function is always enabled. tin0 event input pin for the 16-bit reload timers 0. set the corresponding ddr register to input if this function is used. 48 p57 d general i/o port. this function is enabled when the 16-bit reload timers 0 disables output. tot0 output pin for the 16-bit reload time rs 0. this function is enabled when the 16-bit reload timers 0 enables output. 53 to 58 p70 to p75 d general i/o ports. this function is always enabled. in0 to in5 trigger input pins for input captures icu0 to icu5. set the corre- sponding ddr register to input if this function is used. mb90440g series 10 ds07-13716-3e (continued) pin no. pin name circuit type function 59 to 60 p76 to p77 d general i/o ports. this function is enabled when the ocu disables output. out2 to out3 event output pins for output compares ocu2 and ocu3. this function is enabled when the ocu enables output. in6 to in7 trigger input pins for input captures icu6 and icu7. set the corre- sponiding ddr register to input and prohibit the ocu output if this function is used. 61 to 64 p80 to p83 d general i/o ports. this function is enabled when 8/16-bit ppg timer disables waveform output. ppg0 to ppg3 output pins for 8/16-bit ppg timer. this function is enabled when 8/16-bit ppg timer enables waveform output. 65 to 66 p84 to p85 d general i/o ports. this function is enabled when the ocu disables output. out0 to out1 event output pins for output compares ocu0 and ocu1. this func- tion is enabled when the ocu enables output. 67 p86 d general i/o port. this function is always enabled. tin1 input pin for the 16-bit reload timers 1. set the corresponding ddr register to input if this function is used. 68 p87 d general i/o port. this function is enabled when the 16-bit reload timers 0 disables output. tot1 output pin for the 16-bit reload time rs 1. this function is enabled when the reload timers 1 enables output. 69 to 70 p90 to p91 d general i/o ports. this function is always enabled. int0 to int1 external interrupt request input pins for int0 to int3. set the cor- responding ddr register to input if this function is used. 71 p92 d general i/o port. this function is enabled when can2 disables out- put. tx2 tx output pin for can2. this function is enabled when can2 en- ables output. 72 p93 d general i/o port. this function is always enabled. rx2 rx input pin for can2 interface. when the can function is used, output from the other functions must be stopped. 73 p94 d general i/o port. this function is enabled when can0 disables out- put. tx0 tx output pin for can0. this function is enabled when can0 en- ables output. 74 p95 d general i/o port. this function is always enabled. int2 external interrupt request input pin for int2. set the corresponding ddr register to input if this function is used. rx0 rx input pin for can0 interface. when the can function is used, output from the other functions must be stopped. mb90440g series ds07-13716-3e 11 (continued) input levels the input level of ports p00 to p37 can be selected to be either ttl- or cmos - level. the initial setting is ttl - level. these settings are global for all p00 to p37, it is not possible to set different levels to each port. the input level of ports p40 to pa0 can be selected to be either cmos- or automotive - level. the initial setting is cmos - level. this settings can be done for each port individually. pin no. pin name circuit type function 75 p96 d general i/o port. this function is enabled when can1 disables out- put. tx1 tx output pin for can1. this function is enabled when can1 en- ables output. 76 p97 d general i/o port. this function is always enabled. rx1 rx input pin for can1 interface. when the can function is used, output from the other functions must be stopped. 78 pa0 d general i/o port. this function is always enabled. int3 external interrupt request input pin for int2. set the corresponding ddr register to input if this function is used. 34 av cc power supply power supply pin for t he a/d converter. this power supply must be turned on or off while a voltage higher than or equal to av cc is ap- plied to v cc . 37 av ss power supply dedicated ground pin for the a/d converter 35 avrh power supply external reference voltage pin for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 36 avrl power supply external reference voltage pin for the a/d converter 49 to 50 md0 to md1 c input pins for specifying the oper ating mode. the pins must be di- rectly connected to v cc or vss. 51 md2 f input pin for specifying the operating mode. the pin must be directly connected to v cc or vss. 27 c ? this is the power supply stabilizati on capacitor pin. it should be con- nected externally to an 0.1 f ceramic capacitor. 23, 84 v cc power supply voltage (5.0 v) input pin 11, 42 81 v ss power supply voltage (0.0 v) input pin mb90440g series 12 ds07-13716-3e i/o circuit type (continued) circuit type circuit remarks a oscillation feedback resistor : 1 m ? approx. (high speed oscillator) 10m ? approx. (low speed oscillator) b cmos hysteresis input . pull-up resistor : 50 k ? approx. c hysteresis input d cmos level output cmos hysteresis input automotive hysteresis input (see ? input levels?.) x1, x1a x0,x0a standby control signal osillation feedback resistor hys r (pull-up) r hys r cmos hys autom. hys p-ch v cc n-ch r r mb90440g series ds07-13716-3e 13 (continued) circuit type circuit remarks e cmos level output cmos hysteresis input automotive hysteresis input (see ? input levels?.) analog input f cmos hysteresis input pull-down resistor : 50 k ? approx. (except flash devices) g cmos level output cmos hysteresis input automotive hysteresis input (see ? input levels?.) ttl input (flash devices in flash write mode only) analog input cmos hys autom. hys p-ch n-ch p-ch n-ch r r v cc cmos hys r (pull-down) r cmos hys autom. hys p-ch n-ch r r ttl t r v cc mb90440g series 14 ds07-13716-3e (continued) circuit type circuit remarks h cmos level output cmos hysteresis input ttl hysteresis input (see ? input levels?.) programmable pullup resistor : 50 k ? approx. cmos hys p-ch cntl n-ch r ttl t r v cc v cc mb90440g series ds07-13716-3e 15 handling devices 1. preventing latch-up cmos ic chips may suffer latch-up under the following conditions : (1) a voltage higher than v cc or lower than v ss is applied to an input or output pin. (2) a voltage higher than the rated voltage is applied to between v cc and vss. (3) the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. always take sufficient precau tions in using semiconductor devices to avoid this possibility. also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage (v cc ) when the analog system power-supply is turned on and off. 2. handling unused input pins do not leave unused input pins open, as doing so may cause misoperation of the device or latch-up leading to permanent damage. unused input pins should be pulled up or pulled down through at least 2 k ? resistance. unused i/o pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. use of the external clock to use the external clock, drive only the x0 pin and leave the x1 pin open. a diagram of how to use an external clock is shown below. 4. precautions for when not using a sub clock signal if the x0a and x1a pins are not con nected to an oscillator, apply pull-down treatment to the x0a pin and leave the x1a pin open. 5. power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 f between v cc and v ss pins near the device. x0 x1 open mb90440g series v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90440g series mb90440g series 16 ds07-13716-3e 6. pull-up/down resistors the mb90440g series does not support internal pull-up/down resistors (except pull-up resistors of port 0 to port 3) . use external components needed. 7. crystal oscillator circuit noises around x0 or x1 pins may cause abnormal operat ions. make sure to provide bypass capacitors via the shortest distances from x0 and x1 pins, crystal osc illator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cr oss the lines of other circuits. it is highly recommended to provide a printed circuit bo ard artwork surrounding x0 and x1 pins with a ground area for stabilizing the operation. 8. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d and d/a converters power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning on the digital power supply (v cc ) . turn off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that avrh does not exceed av cc (turning on/off the analog and digital power supplies simultaneously is accept- able) . 9. connection of unused pins of a/d converter connect unused pins of a/d and d/a converters to av cc = v cc , av ss = avrh = v ss . 10. n.c. pin the n.c. (internally connected) pin must be opened for use. 11. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . 12. initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, please turn on the power again. 13. using realos the use of (ei 2 os) is not possible with the realos real time operation system. 14. caution on operations during pll clock mode if the pll clock mode is selected in the microcontroller, it may attempt to continue the operation using the free- running frequency of the automatic oscilla ting circuit in the pll circuitly even if the oscillator is out of place or the clock input is stopped. performance of this operation, however, cannot be guaranteed. mb90440g series ds07-13716-3e 17 block diagram x0, x1 x0a, x1a rst sot0 sck0 sin0 sot1 sck1 sin1 sck2 sot2 sin2 av cc av ss an0 to an7 avrh avrl adtg clock controller ram 6 k prescaler uart0 prescaler prescaler serial i/o 10-bit adc 8 ch uart1 (sci) rom 128 k f mc-16 bus f 2 mc 16lx cpu 16 bit free-run timer 16 bit input capture 8 ch 16 bit output compare 4 ch 8/16-bit ppg timer 4 ch can controller 3 ch 16-bit reload timer 2 ch external bus interface external interrupt circuit 8 ch in6/out2, in7/out3 ad00 to ad15 a16 to a23 int0 to int7 ale rd wrl/wr wrh hrq hak rdy clk rx0 to rx2 tx0 to tx2 tin0, tin1 tot0, tot1 ppg0 to ppg3 in0 to in5 out0, out1 2 mb90440g series 18 ds07-13716-3e memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same address, the table in rom can be referenced without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 48 kbytes, and its entire image cannot be shown in bank 00. the image between ff4000 h and ffffff h is visible in bank 00, while the image between ff4000 h and ffffff h is visible only in bank ff. thus, it is recommended that the rom data table be stored in the area of ff4000 h and ffffff h . rom (fc ba nk) extern a l acce ss extern a l acce ss rom (im a ge of ff ba nk) peripher a l ram 14 k peripher a l rom correction ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h 00ffff h 004000 h 00 3 fff h 00 3 900 h 00 38 ff h 001ff5 h 000100 h 001ff0 h 0000bf h 000000 h rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) extern a l acce ss rom (im a ge of ff ba nk) peripher a l ram 6 k extern a l acce ss extern a l acce ss peripher a l ffffff h ff0000 h feffff h fe0000 h 00ffff h 004000 h 00 3 fff h 00 3 900 h 002000 h 001 8 ff h 000100 h 0000bf h 000000 h rom (ff ba nk) rom (fe ba nk) mb90v440g MB90F443G/ mb90443g (under development) mb90440g series ds07-13716-3e 19 i/o map (continued) address register abbreviation read/ write resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a _______x b 0b h port input levels select register pilr r/w ports 00000000 b 0c h can2 rx/tx pin switching register canswr r/w can1/2 ______00 b 0d h to 0f h reserved 10 h port 0 direction register ddr0 r/w port 0 00000000 b 11 h port 1 direction register ddr1 r/w port 1 00000000 b 12 h port 2 direction register ddr2 r/w port 2 00000000 b 13 h port 3 direction register ddr3 r/w port 3 00000000 b 14 h port 4 direction register ddr4 r/w port 4 00000000 b 15 h port 5 direction register ddr5 r/w port 5 00000000 b 16 h port 6 direction register ddr6 r/w port 6 00000000 b 17 h port 7 direction register ddr7 r/w port 7 00000000 b 18 h port 8 direction register ddr8 r/w port 8 00000000 b 19 h port 9 direction register ddr9 r/w port 9 00000000 b 1a h port a direction register ddra r/w port a _______0 b 1b h analog input enable register ader r/w port 6, a/d 11111111 b 1c h port 0 pullup control register pucr0 r/w port 0 00000000 b 1d h port 1 pullup control register pucr1 r/w port 1 00000000 b 1e h port 2 pullup control register pucr2 r/w port 2 00000000 b 1f h port 3 pullup control register pucr3 r/w port 3 00000000 b 20 h serial mode control register 0 umc0 r/w uart0 00000100 b 21 h serial status register 0 usr0 r/w 00010000 b 22 h serial input/output data register 0 uidr0/uodr0 r/w xxxxxxxx b 23 h rate and data register 0 urd0 r/w 0000000x b mb90440g series 20 ds07-13716-3e (continued) address register abbreviation read/ write resource name initial value 24 h serial mode register 1 smr1 r/w uart1 00000000 b 25 h serial control register 1 scr1 r/w 00000100 b 26 h serial input/output data re gister 1 sidr1/sodr1 r/w xxxxxxxx b 27 h serial status register 1 ssr1 r/w 00001_00 b 28 h uart1 prescaler control register u1cdcr r/w 0___1111 b 29 h serial edge selection registor ses1 r/w _______0 b 2a h reserved 2b h serial i/o prescaler scdcr r/w serial i/o 0___1111 b 2c h serial mode control register smcs r/w ____0000 b 2d h serial mode control register smcs r/w 00000010 b 2e h serial data register sdr r/w xxxxxxxx b 2f h serial edge selection re gistor 2 ses2 r/w _______0 b 30 h external interrupt enable register enir r/w external interrupt circuit 00000000 b 31 h external interrupt requ est register eirr r/w xxxxxxxx b 32 h external request level setting register elvr r/w 00000000 b 33 h 00000000 b 34 h a/d control status register 0 adcs0 r/w a/d converter 00000000 b 35 h a/d control status register 1 adcs1 r/w 00000000 b 36 h a/d data register 0 adcr0 r xxxxxxxx b 37 h a/d data register 1 adcr1 r/w 00001_xx b 38 h ppg0 operation mode control register ppgc0 r/w 16-bit progra- mable pulse generator 0/1 0_000__1 b 39 h ppg1 operation mode control register ppgc1 r/w 0_000001 b 3a h ppg0 and ppg1 clock selection register ppg01 r/w 000000__ b 3b h reserved 3c h ppg2 operation mode control register ppgc2 r/w 16-bit progra- mable pulse generator 2/3 0_000__1 b 3d h ppg3 operation mode control register ppgc3 r/w 0_000001 b 3e h ppg2 and ppg3 clock selection register ppg23 r/w 000000__ b 3f h reserved 40 h ppg4 operation mode control register ppgc4 r/w 16-bit progra- mable pulse generator 4/5 0_000__1 b 41 h ppg5 operation mode control register ppgc5 r/w 0_000001 b 42 h ppg4 and ppg5 clock selection register ppg45 r/w 000000__ b 43 h reserved mb90440g series ds07-13716-3e 21 (continued) address register abbrevia- tion read/ write resource name initial value 44 h ppg6 operation mode control register ppgc6 r/w 16-bit programable pulse generator 6/7 0_000__1 b 45 h ppg7 operation mode control register ppgc7 r/w 0_000001 b 46 h ppg6 and ppg7 clock selection register ppg67 r/w 000000__ b 47 h to 4b h reserved 4c h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 b 4d h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 b 4e h input capture control status 4/5 ics45 r/w input capture 4/5 00000000 b 4f h input capture control status 6/7 ics67 r/w input capture 6/7 00000000 b 50 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 b 51 h ____0000 b 52 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 53 h xxxxxxxx b 54 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 b 55 h ____0000 b 56 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 57 h xxxxxxxx b 58 h output compare control status register 0 ocs0 r/w output compare 0/1 0000__00 b 59 h output compare control status register 1 ocs1 r/w ___00000 b 5a h output compare control status register 2 ocs2 r/w output compare 2/3 0000__00 b 5b h output compare control status register 3 ocs3 r/w ___00000 b 5c h to 6b h reserved for can 2 interface 6c h timer data register tcdt r/w i/o timer 00000000 b 6d h 00000000 b 6e h timer control status register tccs r/w 00000000 b 6f h rom mirror function selection register romm r/w rom mirror function selec- tion module _______1 b 70 h to 7f h reserved for can 0 interface 80 h to 8f h reserved for can 1 interface 90 h to 9d h prohibited area 9e h program address detection control status register pacsr r/w address match detection function 00000000 b 9f h delayed interrupt/rele ase register dirr r/w delayed interrupt genera- tion module _______0 b mb90440g series 22 ds07-13716-3e (continued) address register abbreviation read/ write resource name initial value a0 h low-power consumption mode control register lpmcr r/w low power consumption (stand-by) mode 00011000 b a1 h clock selection register ckscr r/w low power consumption (stand-by) mode 11111100 b a2 h to a4 h prohibited area a5 h automatic ready function select register arsr w external bus pin 0011__00 b a6 h external address output control register hacr w 00000000 b a7 h bus control signal selection register ecsr w 0000000_ b a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx111 b a9 h time base timer control register tbtc r/w time base timer 1- -00100 b aa h watch timer control register wtc r/w watch timer 1x000000 b ab h to ad h prohibited area ae h flash memory control status register (flash only, otherwise reserved) fmcs r/w flash memory 000x0000 b af h prohibited area b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 b b1 h interrupt control register 01 icr01 r/w 00000111 b b2 h interrupt control register 02 icr02 r/w 00000111 b b3 h interrupt control register 03 icr03 r/w 00000111 b b4 h interrupt control register 04 icr04 r/w 00000111 b b5 h interrupt control register 05 icr05 r/w 00000111 b b6 h interrupt control register 06 icr06 r/w 00000111 b b7 h interrupt control register 07 icr07 r/w 00000111 b b8 h interrupt control register 08 icr08 r/w 00000111 b b9 h interrupt control register 09 icr09 r/w 00000111 b ba h interrupt control register 10 icr10 r/w 00000111 b bb h interrupt control register 11 icr11 r/w 00000111 b bc h interrupt control register 12 icr12 r/w 00000111 b bd h interrupt control register 13 icr13 r/w 00000111 b be h interrupt control register 14 icr14 r/w 00000111 b bf h interrupt control register 15 icr15 r/w 00000111 b c0 h to ff h external mb90440g series ds07-13716-3e 23 (continued) (continued) address register abbreviation read/ write resource name initial value 1ff0 h program address detection register 0 padr0 r/w address match detection function xxxxxxxx b 1ff1 h r/w xxxxxxxx b 1ff2 h r/w xxxxxxxx b 1ff3 h program address detection register 1 padr1 r/w xxxxxxxx b 1ff4 h r/w xxxxxxxx b 1ff5 h r/w xxxxxxxx b address register abbreviation read/ write resource name initial value 3900 h reload register l prll0 r/w 16-bit programable pulse generator 0/1 xxxxxxxx b 3901 h reload register h prlh0 r/w xxxxxxxx b 3902 h reload register l prll1 r/w xxxxxxxx b 3903 h reload register h prlh1 r/w xxxxxxxx b 3904 h reload register l prll2 r/w 16-bit programable pulse generator 2/3 xxxxxxxx b 3905 h reload register h prlh2 r/w xxxxxxxx b 3906 h reload register l prll3 r/w xxxxxxxx b 3907 h reload register h prlh3 r/w xxxxxxxx b 3908 h reload register l prll4 r/w 16-bit programable pulse generator 4/5 xxxxxxxx b 3909 h reload register h prlh4 r/w xxxxxxxx b 390a h reload register l prll5 r/w xxxxxxxx b 390b h reload register h prlh5 r/w xxxxxxxx b 390c h reload register l prll6 r/w 16-bit programable pulse generator 6/7 xxxxxxxx b 390d h reload register h prlh6 r/w xxxxxxxx b 390e h reload register l prll7 r/w xxxxxxxx b 390f h reload register h prlh7 r/w xxxxxxxx b 3910 h to 3917 h reserved 3918 h input capture register 0 ipcp0 r input captue 0/1 xxxxxxxx b 3919 h input captur e register 0 ipcp0 r xxxxxxxx b 391a h input captur e register 1 ipcp1 r xxxxxxxx b 391b h input captur e register 1 ipcp1 r xxxxxxxx b 391c h input capture register 2 ipcp2 r input captue 2/3 xxxxxxxx b 391d h input captur e register 2 ipcp2 r xxxxxxxx b 391e h input captur e register 3 ipcp3 r xxxxxxxx b 391f h input captur e register 3 ipcp3 r xxxxxxxx b mb90440g series 24 ds07-13716-3e (continued) meaning of abbreviations used for reading and writing explanation of initial values note : addresses in the range 0000 h to 00ff h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results reading ?x? and any write access should not be performed. address register abbreviation read/ write resource name initial value 3920 h input capture register 4 ipcp4 r input captue 4/5 xxxxxxxx b 3921 h input captur e register 4 ipcp4 r xxxxxxxx b 3922 h input captur e register 5 ipcp5 r xxxxxxxx b 3923 h input captur e register 5 ipcp5 r xxxxxxxx b 3924 h input capture register 6 ipcp6 r input captue 6/7 xxxxxxxx b 3925 h input captur e register 6 ipcp6 r xxxxxxxx b 3926 h input captur e register 7 ipcp7 r xxxxxxxx b 3927 h input captur e register 7 ipcp7 r xxxxxxxx b 3928 h output compare register 0 occp0 r/w output compare 0/1 xxxxxxxx b 3929 h output compare register 0 occp0 r/w xxxxxxxx b 392a h output compare register 1 occp1 r/w xxxxxxxx b 392b h output compare register 1 occp1 r/w xxxxxxxx b 392c h output compare register 2 occp2 r/w output compare 2/3 xxxxxxxx b 392d h output compare register 2 occp2 r/w xxxxxxxx b 392e h output compare register 3 occp3 r/w xxxxxxxx b 392f h output compare register 3 occp3 r/w xxxxxxxx b 3930 h to 39ff h reserved 3a00 h to 3aff h reserved for can 0 interface 3b00 h to 3bff h reserved for can 0 interface 3c00 h to 3cff h reserved for can 1 interface 3d00 h to 3dff h reserved for can 1 interface 3e00 h to 3eff h reserved for can 2 interface 3f00 h to 3fff h reserved for can 2 interface r/w : read and write enabled r : read only w : write only 0 : the bit is initialized to 0. 1 : the bit is initialized to 1. x : the initial value of the bit is undefined. _ : the bit is not used. its initial value is undefined. mb90440g series ds07-13716-3e 25 can controller the mb90440g series contains three generic can controllers (can0, can1, can2) . the can controller has the following features : conforms to can specification version 2.0 part a and b - supports transmission/reception in standard frame and extended frame formats supports transmission of data frames by receiving remote frames 16 transmission/reception message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as id acceptance mask - two acceptance mask registers in either standard frame format or extended frame formats bit rate programmable from 10 kbps to 1 mbps (when input clock is at 16 mhz) list of control registers (continued) address register abbreviation read/ write initial value can0 can1 can2 000070 h 000080 h 00005c h message buffer va lid register bvalr r/w 00000000 00000000 b 000071 h 000081 h 00005d h 000072 h 000082 h 00005e h transmit request register treqr r/w 00000000 00000000 b 000073 h 000083 h 00005f h 000074 h 000084 h 000060 h transmit cancel register tcanr w 00000000 00000000 b 000075 h 000085 h 000061 h 000076 h 000086 h 000062 h transmit complete register tcr r/w 00000000 00000000 b 000077 h 000087 h 000063 h 000078 h 000088 h 000064 h receive complete register rcr r/w 00000000 00000000 b 000079 h 000089 h 000065 h 00007a h 00008a h 000066 h remote request receiving register rrtrr r/w 00000000 00000000 b 00007b h 00008b h 000067 h 00007c h 00008c h 000068 h receive overrun register rovrr r/w 00000000 00000000 b 00007d h 00008d h 000069 h 00007e h 00008e h 00006a h receive interrupt enable register rier r/w 00000000 00000000 b 00007f h 00008f h 00006b h 003b00 h 003d00 h 003f00 h control status register csr r/w, r 00---000 0----0- 1 b 003b01 h 003d01 h 003f01 h 003b02 h 003d02 h 003f02 h last event indicator register leir r/w -------- 000- 0000 b 003b03 h 003d03 h 003f03 h 003b04 h 003d04 h 003f04 h receive/tran smit error counter rtec r 00000000 00000000 b 003b05 h 003d05 h 003f05 h mb90440g series 26 ds07-13716-3e (continued) address register abbreviation read/ write initial value can0 can1 can2 003b06 h 003d06 h 003f06 h bit timing register btr r/w -1111111 11111111 b 003b07 h 003d07 h 003f07 h 003b08 h 003d08 h 003f08 h ide register ider r/w xxxxxxxx xxxxxxxx b 003b09 h 003d09 h 003f09 h 003b0a h 003d0a h 003f0a h transmit rtr register trtrr r/w 00000000 00000000 b 003b0b h 003d0b h 003f0b h 003b0c h 003d0c h 003f0c h remote frame re ceive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 003b0d h 003d0d h 003f0d h 003b0e h 003d0e h 003f0e h transmit interrupt enable register tier r/w 00000000 00000000 b 003b0f h 003d0f h 003f0f h 003b10 h 003d10 h 003f10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx b 003b11 h 003d11 h 003f11 h 003b12 h 003d12 h 003f12 h xxxxxxxx xxxxxxxx b 003b13 h 003d13 h 003f13 h 003b14 h 003d14 h 003f14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 003b15 h 003d15 h 003f15 h 003b16 h 003d16 h 003f16 h xxxxx--- xxxxxxxx b 003b17 h 003d17 h 003f17 h 003b18 h 003d18 h 003f18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 003b19 h 003d19 h 003f19 h 003b1a h 003d1a h 003f1a h xxxxx--- xxxxxxxx b 003b1b h 003d1b h 003f1b h mb90440g series ds07-13716-3e 27 list of message buffers ( id registers ) (continued) address register abbreviation read/ write initial value can0 can1 can2 003a00 h to 003a1f h 003c00 h to 003c1f h 003e00 h to 003e1f h ram area ? r/w xxxxxxxx b to xxxxxxxx b 003a20 h 003c20 h 003e20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 003a21 h 003c21 h 003e21 h 003a22 h 003c22 h 003e22 h xxxxx--- xxxxxxxx b 003a23 h 003c23 h 003e23 h 003a24 h 003c24 h 003e24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 003a25 h 003c25 h 003e25 h 003a26 h 003c26 h 003e26 h xxxxx--- xxxxxxxx b 003a27 h 003c27 h 003e27 h 003a28 h 003c28 h 003e28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 003a29 h 003c29 h 003e29 h 003a2a h 003c2a h 003e2a h xxxxx--- xxxxxxxx b 003a2b h 003c2b h 003e2b h 003a2c h 003c2c h 003e2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 003a2d h 003c2d h 003e2d h 003a2e h 003c2e h 003e2e h xxxxx--- xxxxxxxx b 003a2f h 003c2f h 003e2f h 003a30 h 003c30 h 003e30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 003a31 h 003c31 h 003e31 h 003a32 h 003c32 h 003e32 h xxxxx--- xxxxxxxx b 003a33 h 003c33 h 003e33 h 003a34 h 003c34 h 003e34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 003a35 h 003c35 h 003e35 h 003a36 h 003c36 h 003e36 h xxxxx--- xxxxxxxx b 003a37 h 003c37 h 003e37 h 003a38 h 003c38 h 003e38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 003a39 h 003c39 h 003e39 h 003a3a h 003c3a h 003e3a h xxxxx--- xxxxxxxx b 003a3b h 003c3b h 003e3b h mb90440g series 28 ds07-13716-3e (continued) address register abbreviation read/ write initial value can0 can1 can2 003a3c h 003c3c h 003e3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 003a3d h 003c3d h 003e3d h 003a3e h 003c3e h 003e3e h xxxxx--- xxxxxxxx b 003a3f h 003c3f h 003e3f h 003a40 h 003c40 h 003e40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 003a41 h 003c41 h 003e41 h 003a42 h 003c42 h 003e42 h xxxxx--- xxxxxxxx b 003a43 h 003c43 h 003e43 h 003a44 h 003c44 h 003e44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 003a45 h 003c45 h 003e45 h 003a46 h 003c46 h 003e46 h xxxxx--- xxxxxxxx b 003a47 h 003c47 h 003e47 h 003a48 h 003c48 h 003e48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 003a49 h 003c49 h 003e49 h 003a4a h 003c4a h 003e4a h xxxxx--- xxxxxxxx b 003a4b h 003c4b h 003e4b h 003a4c h 003c4c h 003e4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 003a4d h 003c4d h 003e4d h 003a4e h 003c4e h 003e4e h xxxxx--- xxxxxxxx b 003a4f h 003c4f h 003e4f h 003a50 h 003c50 h 003e50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 003a51 h 003c51 h 003e51 h 003a52 h 003c52 h 003e52 h xxxxx--- xxxxxxxx b 003a53 h 003c53 h 003e53 h 003a54 h 003c54 h 003e54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 003a55 h 003c55 h 003e55 h 003a56 h 003c56 h 003e56 h xxxxx--- xxxxxxxx b 003a57 h 003c57 h 003e57 h 003a58 h 003c58 h 003e58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 003a59 h 003c59 h 003e59 h 003a5a h 003c5a h 003e5a h xxxxx--- xxxxxxxx b 003a5b h 003c5b h 003e5b h mb90440g series ds07-13716-3e 29 (continued) list of message buffers ( dlc registers and data registers ) (continued) address register abbreviation read/ write initial value can0 can1 can2 003a5c h 003c5c h 003e5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 003a5d h 003c5d h 003e5d h 003a5e h 003c5e h 003e5e h xxxxx--- xxxxxxxx b 003a5f h 003c5f h 003e5f h address register abbreviation read/ write initial value can0 can1 can2 003a60 h 003c60 h 003e60 h dlc register 0 dlcr0 r/w ----xxxx b 003a61 h 003c61 h 003e61 h 003a62 h 003c62 h 003e62 h dlc register 1 dlcr1 r/w ----xxxx b 003a63 h 003c63 h 003e63 h 003a64 h 003c64 h 003e64 h dlc register 2 dlcr2 r/w ----xxxx b 003a65 h 003c65 h 003e65 h 003a66 h 003c66 h 003e66 h dlc register 3 dlcr3 r/w ----xxxx b 003a67 h 003c67 h 003e67 h 003a68 h 003c68 h 003e68 h dlc register 4 dlcr4 r/w ----xxxx b 003a69 h 003c69 h 003e69 h 003a6a h 003c6a h 003e6a h dlc register 5 dlcr5 r/w ----xxxx b 003a6b h 003c6b h 003e6b h 003a6c h 003c6c h 003e6c h dlc register 6 dlcr6 r/w ----xxxx b 003a6d h 003c6d h 003e6d h 003a6e h 003c6e h 003e6e h dlc register 7 dlcr7 r/w ----xxxx b 003a6f h 003c6f h 003e6f h 003a70 h 003c70 h 003e70 h dlc register 8 dlcr8 r/w ----xxxx b 003a71 h 003c71 h 003e71 h 003a72 h 003c72 h 003e72 h dlc register 9 dlcr9 r/w ----xxxx b 003a73 h 003c73 h 003e73 h 003a74 h 003c74 h 003e74 h dlc register 10 dlcr10 r/w ----xxxx b 003a75 h 003c75 h 003e75 h 003a76 h 003c76 h 003e76 h dlc register 11 dlcr11 r/w ----xxxx b 003a77 h 003c77 h 003e77 h mb90440g series 30 ds07-13716-3e (continued) address register abbreviation read/ write initial value can0 can1 can2 003a78 h 003c78 h 003e78 h dlc register 12 dlcr12 r/w ----xxxx b 003a79 h 003c79 h 003e79 h 003a7a h 003c7a h 003e7a h dlc register 13 dlcr13 r/w ----xxxx b 003a7b h 003c7b h 003e7b h 003a7c h 003c7c h 003e7c h dlc register 14 dlcr14 r/w ----xxxx b 003a7d h 003c7d h 003e7d h 003a7e h 003c7e h 003e7e h dlc register 15 dlcr15 r/w ----xxxx b 003a7f h 003c7f h 003e7f h 003a80 h to 003a87 h 003c80 h to 003c87 h 003e80 h to 003e87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 003a88 h to 003a8f h 003c88 h to 003c8f h 003e88 h to 003e8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 003a90 h to 003a97 h 003c90 h to 003c97 h 003e90 h to 003e97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 003a98 h to 003a9f h 003c98 h to 003c9f h 003e98 h to 003e9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 003aa0 h to 003aa7 h 003ca0 h to 003ca7 h 003ea0 h to 003ea7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 003aa8 h to 003aaf h 003ca8 h to 003caf h 003ea8 h to 003eaf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 003ab0 h to 003ab7 h 003cb0 h to 003cb7 h 003eb0 h to 003eb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b mb90440g series ds07-13716-3e 31 (continued) address register abbreviation read/ write initial value can0 can1 can2 003ab8 h to 003abf h 003cb8 h to 003cbf h 003eb8 h to 003ebf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 003ac0 h to 003ac7 h 003cc0 h to 003cc7 h 003ec0 h to 003ec7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 003ac8 h to 003acf h 003cc8 h to 003ccf h 003ec8 h to 003ecf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 003ad0 h to 003ad7 h 003cd0 h to 003cd7 h 003ed0 h to 003ed7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 003ad8 h to 003adf h 003cd8 h to 003cdf h 003ed8 h to 003edf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 003ae0 h to 003ae7 h 003ce0 h to 003ce7 h 003ee0 h to 003ee7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 003ae8 h to 003aef h 003ce8 h to 003cef h 003ee8 h to 003eef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 003af0 h to 003af7 h 003cf0 h to 003cf7 h 003ef0 h to 003ef7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 003af8 h to 003aff h 003cf8 h to 003cff h 003ef8 h to 003eff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b mb90440g series 32 ds07-13716-3e interrupt factors, interrupt vect ors, interrupt control register (continued) interrupt cause ei 2 os support interrupt vector interrupt control register number address number address reset n/a #08 ffffdc h ?? int9 instruction n/a #09 ffffd8 h ?? exception processing n/a #10 ffffd4 h ?? can 0 receive n/a #11 ffffd0 h icr00 0000b0 h can 0 transmit/node status n/a #12 ffffcc h can 1 receive n/a #13 ffffc8 h icr01 0000b1 h can 1 transmit/node status n/a #14 ffffc4 h external interrupt (int0/int1) *1 #15 ffffc0 h icr02 0000b2 h timebase timer n/a #16 ffffbc h 16-bit reload timer 0 *1 #17 ffffb8 h icr03 0000b3 h 8/10-bit a/d converter *1 #18 ffffb4 h 16-bit free-run timer n/a #19 ffffb0 h icr04 0000b4 h external interrupt (int2/int3) *1 #20 ffffac h serial i/o *1 #21 ffffa8 h icr05 0000b5 h 8/16-bit ppg timer 0/1/2/3 n/a #22 ffffa4 h input capture 0 *1 #23 ffffa0 h icr06 0000b6 h external interrupt (int4/int5) *1 #24 ffff9c h can 2 receive n/a #25 ffff98 h icr07 0000b7 h can 2 transmit/node status n/a #26 ffff94 h external interrupt (int6/int7) *1 #27 ffff90 h icr08 0000b8 h monitoring timer n/a #28 ffff8c h input capture 1 *1 #29 ffff88 h icr09 0000b9 h input capture 2/3 *1 #30 ffff84 h 8/16-bit ppg timer 4/5/6/7 n/a #31 ffff80 h icr10 0000ba h output compare 0 *1 #32 ffff7c h output compare 1 *1 #33 ffff78 h icr11 0000bb h input capture 4/5 *1 #34 ffff74 h output compare 2/3-input capture 6/7 *1 #35 ffff70 h icr12 0000bc h 16-bit reload timer 1 *1 #36 ffff6c h uart 0 receive *2 #37 ffff68 h icr13 0000bd h uart 0 transmit *1 #38 ffff64 h uart 1 receive *2 #39 ffff60 h icr14 0000be h uart 1 transmit *1 #40 ffff5c h mb90440g series ds07-13716-3e 33 (continued) notes : ? n/a : the interrupt request flag is not cleared by the ei 2 os interrupt clear signal. ? for a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the ei 2 os interrupt clear signal. ? at the end of ei 2 os, the ei 2 os clear signal will be asserted for all th e interrupt flags assigned to the same interrupt number. if one interrupt flag starts the ei 2 os and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the ei 2 os clear signal caused by the first event. so it is recommended not to use the ei 2 os for this interrupt number. ? if ei 2 os is enabled, ei 2 os is initiated when one of the two interrupt signals in the same interrupt control register (icr) is asserted. this means that different interrupt causes share the same ei 2 os descriptor which should be unique for each interrupt cause. for this reason, when one interrupt cause uses the ei 2 os, the other interrupt should be disabled. interrupt cause ei 2 os support interrupt vector interrupt control register number address number address flash memory n/a #41 ffff58 h icr15 0000bf h delayed interrupt generation module n/a #42 ffff54 h h *1 : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. *2 : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. a stop request is available. mb90440g series 34 ds07-13716-3e electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc , avrh, and avrl shall never exceed v cc . avrh, avrl shall never exceed av cc . also, avrl shall never exceed avrh. *2 : v i and v o shall never exceed v cc + 0.3 v. v i shall never exceed the specified ratings. however if the maximum current to/ from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *3 : maximum output current specifies the peak value of the corresponding pin. *4 : the average output current specifies the average current of corresponding pins within 100 ms. (operation current operation rate = average value) *5 : the total average output current specifies the average current of all corresponding pins within 100 ms. (operation current operation rate = average value) *6 : ? applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 ? use within recommended operating conditions. ? use at dc voltage (current) . (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 1 avrh, avrl v ss ? 0.3 v ss + 6.0 v av cc avrh / avrl, avrh avrl *1 input voltage v i v ss ? 0.3 v ss + 6.0 v *2 output voltage v o v ss ? 0.3 v ss + 6.0 v *2 maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current ? i clamp ? ? 20 ma *6 ?l? level maximum output current i ol ? 15 ma *3 ?l? level average output current i olav ? 4ma *4 ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma *5 ?h? level maximum output current i oh ?? 15 ma *3 ?h? level average output current i ohav ?? 4ma *4 ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma *5 power consumption p d ? 500 mw MB90F443G ? 400 mw MB90F443G (under development) operating temperature t a ? 40 + 105 c storage temperature tstg ? 55 + 150 c mb90440g series ds07-13716-3e 35 (continued) ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode mb90440g series 36 ds07-13716-3e 2. recommended operating conditions (v ss = av ss = 0.0 v) * : use a ceramic capacitor or capacitor of be tter ac characteristics. capacitor at the v cc should be greater than this capacitor. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ranges ma y adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outsi de the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.5 5.0 5.5 v under normal operation 3.0 ? 5.5 v retains status at the time of opera- tion stop smoothing capacitor c s 0.022 0.1 1.0 f* operating temperature t a ? 40 ?+ 105 c c c s c pin connection circuit mb90440g series ds07-13716-3e 37 3. dc characteristics (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (continued) parameter symbol pin condition value unit remarks min typ max input h voltage v ihs cmos hysteresis input pin ? 0.8 v cc ? v cc + 0.3 v v iha automotive input pin ? 0.8 v cc ?? v v ih ttl input pin ? 2.0 ?? v v ihm md input pin ? v cc ? 0.3 ? v cc + 0.3 v input l voltage v ils cmos hysteresis input pin ? v ss ? 0.3 ? 0.2 v cc v v ila automotive input pin ??? 0.5 v cc v v il ttl input pin ??? 0.8 v v ilm md input pin ? v ss ? 0.3 ? v ss + 0.3 v output h voltage v oh all output pins v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v output l voltage v ol all output pins v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v input leak current i il ? v cc = 5.5 v, v ss < v i < v cc ? 5 ? + 5 a mb90440g series 38 ds07-13716-3e (continued) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : the power supply current is measured with an external clock. parameter symbol pin condition value unit remarks min typ max power supply current * i cc v cc v cc = 5.0 v internal frequency : 16 mhz, at normal operating ? 45 60 ma v cc = 5.0 v internal frequency : 16 mhz, at flash programming / erasing ? 50 70 ma i ccs v cc = 5.0 v internal frequency : 16 mhz, at sleep ? 13 22 ma i ccl v cc = 5.0 v internal frequency : 8 khz, at sub operation t a = + 25 c ? 50 100 a mb90443g (under devel- opment) ? 300 500 a MB90F443G i ccls v cc = 5.0 v internal frequency : 8 khz, at sub sleep t a = + 25 c ? 15 40 a i cct v cc = 5.0 v internal frequency : 8 khz, at watch mode t a = + 25 c ? 725 a i cts v cc = 5.0 v internal frequency : 2 mhz, at timer base timer mode t a = + 25 c ? 600 1200 a i cch at stop mode, t a = + 25 c ? 520 a input capacity c in other than av cc , av ss , avrh, avrl, c, v cc , v ss ?? 10 15 pf pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? mb90440g series ds07-13716-3e 39 4. ac characteristics (1) clock timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : when selecting the pll clock, the range of clock frequency is limitted. use this product within range as mentioned in " ? guaranteed pll operation rang e : relationship between oscilla tion frequency and internal operating clock frequency". parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz not multiplied 8 ? 16 mhz pll multiplied by 1* 4 ? 8 mhz pll multiplied by 2* 3 ? 5.33 mhz pll multiplied by 3* 3 ? 4 mhz pll multiplied by 4* f cl x0a, x1a ? 32.768 ? khz clock cycle time t cyl x0, x1 62.5 ? 333 ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p wlh , p wll x0a ? 15.2 ? s input clock rise and fall time t cr , t cf x0 ?? 5ns when using external clock internal operating clock frequency f cp ? 1.5 ? 16 mhz when using main clock f lcp ?? 8.192 ? khz when using sub-clock internal operating clock cycle time t cp ? 62.5 ? 666 ns when using main clock t lcp ?? 122.1 ? s when using sub-clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll clock timing mb90440g series 40 ds07-13716-3e the ac ratings are measured for the following measurement reference voltages. 5.5 4.5 8 1.5 16 guaranteed operation range power supply voltage v cc (v) internal clock f cp (mhz) guaranteed pll operation range 16 12 8 9 4 34 8 16 not multiplied 4 3 2 1 internal clock f cp (mhz) oscillation frequency f c (mhz) guaranteed pll operation range relationship between internal operation clock frequency and power supply voltage relationship between oscilla tion frequency and internal operating clock frequency 0.8 v cc 0.2 v cc 2.4 v 0.8 v 2.0 v 0.8 v 0.8 v cc 0.5 v cc cmos hysteresis input pin output pin ttl input pin automotive input pin input signal waveform output signal waveform mb90440g series ds07-13716-3e 41 (2) clock output timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin condition value unit remarks min max cycle time t cyc clk v cc = 5 v 10 % 62.5 ? ns clk clk t chcl 20 ? ns clk t cyc 2.4 v 2.4 v 0.8 v t chcl mb90440g series 42 ds07-13716-3e (3) reset input timing and hardware stand-by input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) note: ? oscillator oscillation time is th e time that amp litude reached 90 % . for a crystal oscilla tor, the oscillation time is between several ms to tens of ms; for a ceramic oscillator, the o scillation time is between hundreds of s to several ms, and for an external clock the oscillation time is 0 ms. ? any reset can not fully initialize the flash memory if it is performing the automatic algorithm. parameter symbol pin value unit remarks min max reset input time t rstl rst 16 t cp ? ns under normal operation oscillation time of oscillator + 100 s + 16 t cp ?? in stop mode, watch mode, sub-clock mode, sub-sleep mode rst 0.2 v cc t rstl 0.2 v cc t rstl 0.2 v cc 0.2 v cc rst x0 90% of amplitude instruction execution oscillation setting time oscillator oscillation time internal operation clock internal reset in stop mode : under normal operation : 100 s + 16 t cp mb90440g series ds07-13716-3e 43 (4) power-on reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : v cc must be kept lower than 0.2 v before power-on. note : the above values are used for causing a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these registers, turn the power supply on using the above values. parameter symbol pin condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms * power supply cut-off time t off v cc 50 ? ms due to repeated operations v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v ram data hold sudden changes in the power supply voltage may cause a power on reset. we recommend to raise the voltage smoothly to suppress fluctuation during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. we recommend rising speed of the supply voltage at 50 mv/ms or slower mb90440g series 44 ds07-13716-3e (5) bus timing (read) (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin value unit remarks min max ale pulse width t lhll ale t cp / 2 ? 20 ? ns valid address ale time t avll ale, a16 to a23, ad00 to ad15 t cp / 2 ? 20 ? ns ale address valid time t llax ale, ad00 to ad15 t cp / 2 ? 15 ? ns valid address rd time t avrl a16 to a23, ad00 to ad15, rd t cp ? 15 ? ns valid address valid data input t avdv a16 to a23, ad00 to ad15 ? 5 t cp / 2 ? 60 ns rd pulse width t rlrh rd 3 t cp / 2 ? 20 ? ns rd valid data input t rldv r d , ad00 to ad15 ? 3 t cp / 2 ? 60 ns rd data hold time t rhdx rd , ad00 to ad15 0 ? ns rd ale time t rhlh rd , ale t cp / 2 ? 15 ? ns rd address valid time t rhax rd , a16 to a23 t cp / 2 ? 10 ? ns valid address clk time t avch a16 to a23, ad00 to ad15, clk t cp / 2 ? 20 ? ns rd clk time t rlch rd , clk t cp / 2 ? 20 ? ns ale rd time t llrl ale, rd t cp / 2 ? 15 ? ns mb90440g series ds07-13716-3e 45 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.2 v cc 0.8 v cc clk ale rd a23 to a16 ad15 to ad00 t rhlh t avrl t avll t llax t lhll t rlrh t rhax t rhdx t rlch 2.4 v 2.4 v 0.8 v t avch 0.2 v cc 0.8 v cc t avdv t rldv 2.4 v t llrl address read data bus timing ( read ) mb90440g series 46 ds07-13716-3e (6) bus timing (write) (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin value unit remarks min max valid address wr time t avwl a16 to a23, ad00 to ad15, wr t cp ? 15 ? ns wr pulse width t wlwh wr 3 t cp / 2 ? 20 ? ns valid data output wr time t dvwh ad00 to ad15, wr 3 t cp / 2 ? 20 ? ns wr data hold time t whdx ad00 to ad15, wr 20 ? ns wr address valid time t whax a16 to a23, wr t cp / 2 ? 10 ? ns wr ale time t whlh wr , ale t cp / 2 ? 15 ? ns wr clk time t wlch wr , clk t cp / 2 ? 20 ? ns 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale wr (wrl, wrh) a23 to a16 ad15 to ad00 t whl t avwl t wlwh t whax t whdx t wlc t dvwh address write data bus timing ( write ) mb90440g series ds07-13716-3e 47 (7) ready input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) note : if the rdy setup time is insufficient, use the auto-ready function. parameter symbol pin value unit remarks min max rdy setup time t ryhs rdy 45 ? ns rdy hold time t ryhh rdy 0 ? ns t ryhs t ryhh 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc clk ale rd/wr rdy no wait is used. rdy when wait is used (1 cycle). ready input timing mb90440g series 48 ds07-13716-3e (8) hold timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) note : more than 1 machine cycle is needed before hak changes after hrq pin is fetched. parameter symbol pin value unit remarks min max pin floating hak time t xhal hak 30 t cp ns hak pin valid time t hahv hak t cp 2 t cp ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v each pin high impedance hold timing mb90440g series ds07-13716-3e 49 (9) uart0/1, serial i/o timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) notes : ? ac ratings in clk synchronous mode. ? c l is load capacitance value c onnected to pins when testing. parameter symbol pin condition value unit remarks min max serial clock cycle time t scyc sck0 to sck2 an output pin of internal sift clock mode c l = 80 pf + 1 ttl. 4 t cp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ?80 + 80 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 100 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck2 an output pin of external sift clock mode c l = 80 pf + 1 ttl. 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck2 4 t cp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ? 150 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 60 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns mb90440g series 50 ds07-13716-3e sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc external shift clock mode mb90440g series ds07-13716-3e 51 (10) timer related resource input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin condition value unit remarks min max input pulse width t tiwh tin0, tin1 ? 4 t cp ? ns t tiwl in0 to in7 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tin0, tin1 in0 to in7 timer input timing mb90440g series 52 ds07-13716-3e (11) timer related resource output timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) (12) trigger input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin condition value unit remarks min max clk t out transition time t to tot0 to tot1, ppg0 to ppg3 ? 30 ? ns parameter symbol pin condition value unit remarks min max input pulse width t trgh t trgl int0 to int7, adtg ? 5 t cp ? ns normal operation 1 ? sstop mode 2.4 v t to 2.4 v 0.8 v clk t out timer output timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl int0 to int7 adtg trigger input timing mb90440g series ds07-13716-3e 53 5. a/d converter electrical characteristics (v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, 3.0 v avrh ? avrl, t a = ? 40 c to + 105 c) * : specifies the power supply current (v cc = av cc = avrh = 5.0 v) when the a/d converter is inactive and the cpu has been stopped. parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 5.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 avrl ? 3.5 lsb avrl + 0.5 lsb avrl + 4.5 lsb v 1 lsb = (avrh ? avrl) / 1024 [v] full scale transition voltage v fst an0 to an7 avrh ? 6.5 lsb avrh ? 1.5 lsb avrh + 1.5 lsb v compare time ?? 66 t cp ?? ns machine clock of 16 mhz sampling time ?? 32 t cp ?? ns analog port input current i ain an0 to an7 ?? 10 a analog input voltage v ain an0 to an7 avrl ? avrh v reference voltage ? avrh avrl + 2.7 lsb ? av cc v ? avrl 0 ? avrh ? 2.7 lsb v power supply current i a av cc ? 26ma i ah av cc ?? 5 a* reference voltage supply current i r avrh ? 0.9 1.3 ma i rh avrh ?? 5 a* offset between channels ? an0 to an7 ?? 4lsb mb90440g series 54 ds07-13716-3e ? a / d converter glossary (continued) resolution : analog changes that are identifiable with the a/d converter linearity error : the deviation of the straight line connecting the zero transition point ( ?00 0000 0000? to ?00 0000 0001? ) with the full-scale transition point ( ?11 1111 1110? to ?11 1111 1111? ) from actual conversion characteristics. differential linearity error : the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. total error : the difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, and linearity error. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (measured value) actual conversion characteristics theoretical characteristics digital output analog input total error total error of digital output n = v nt ? {1 lsb x (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (theoretical value) avrh ? avrl 1024 [v] v ot (theoretical value) = avrl + 0.5 lsb [v] v fst (theoretical value) = avrh ? 1.5 lsb [v] v nt : the voltage at a transition of digital output from (n ? 1) to n. mb90440g series ds07-13716-3e 55 (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v nt v ot ( measured value ) v fst {1 lsb (n ? 1) + v ot } actual conversion characteristics (measured value) (measured value) actual conversion characteristics theoretical characteristics actual conversion characteristics actual conversion characteristics theoretical characteristics digital output digital output analog input analog input v nt (measured value) v (n + 1) t (measured value) linearity error differe ntial linearity error linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity erro r of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output 000 h to 001 h . v fst : voltage at transition of digital output 3fe h to 3ff h . mb90440g series 56 ds07-13716-3e ? notes on using a / d converter select the output impedance value for the external circuit of analog input according to the following conditions : output impedance values of the external circuit of about 5 k ? or lower are recommended. if external capacitors are used, a capacitance of severa l thousand times the internal capacitor value is recom- mended in order to minimize the effect of voltage dist ribution between the external and internal capacitor. note: if the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling period = 2.00 s @ machine clock of 16 mhz) . the output impedance of the external circuit can be set to approx. 15k ? or lower , when the sampling period is set to 4.00 s. about error the smaller the absolute value of | avrh ? avrl | is, the greater the relative error is. 6. flash memory program/erase characteristics parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 5 ? s excludes 00h programming prior erasure word (16 bit width) programming time ? 16 3,600 s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle c comparator analog input r MB90F443G, mb90v440g r : = 3.2 k ? , c : = 30 pf mb90443g (under development) r : = 2.6 k ? , c : = 28 pf analog input circuit model mb90440g series ds07-13716-3e 57 example characteristics ? ?h? level output voltage ? ?l? level output voltage 3.5 3 2.5 2 1.5 1 0.5 0 -2.0 -10.0 -8.0 -6.0 -4.0 i oh [ma] v oh [v] v oh ? i oh (vcc = 4.5 v, ta = +25?c) 4.5 4 0.0 0.8 0.7 0.6 0.5 0.4 0.2 0 i ol [ma] v ol [mv] v ol ? i ol (v cc = 4.5 v, ta = +25?c) 0.0 10.0 8.0 6.0 4.0 2.0 0.3 0.1 mb90440g series 58 ds07-13716-3e ? power supply current (flash) 12 10 8 6 4 2 0 iccs [ma] 12 10 8 6 4 2 0 i cct [ a] 14 16 18 20 600 500 400 300 200 100 0 vcc [v] i cts [ a] i cts ? v cc (fcp = 2 mhz, ta = +25?c) vcc [v] i cch ? v cc (ta = +25?c) 40 35 30 25 20 15 10 5 0 2.0 7.0 6.0 5.0 4.0 3.0 vcc [v] icc [ma] icc ? vcc fcp = 12 mhz fcp = 16 mhz fcp = 10 mhz fcp = 4 mhz fcp = 2 mhz (ta = +25?c) 50 45 fcp = 8 mhz vcc [v] iccs ? vcc fcp = 12 mhz fcp = 16 mhz fcp = 10 mhz fcp = 2 mhz (ta = +25?c) 2.0 7.0 6.0 5.0 4.0 3.0 2.0 7.0 6.0 5.0 4.0 3.0 fcp = 4 mhz fcp = 8 mhz 2.0 7.0 6.0 5.0 4.0 3.0 14 16 18 20 mb90440g series ds07-13716-3e 59 ordering information part number package remarks mb90443gpf (under development) MB90F443Gpf 100-pin plastic qfp (fpt-100p-m06) mb90v440gcr 256-pin ceramic pga (pga-256c-a01) for evaluation mb90440g series 60 ds07-13716-3e package dimensions please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2002-200 8 fujit s u microelectronic s limited f10000 8s -c-5-6 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. mb90440g series ds07-13716-3e 61 main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 4 product lineup changed the resource name. 16-bit i/o timer 16-bit free-run timer 6 pin assignment cha nged the pin name. 35-pin : avr + avrh 36-pin : avr - avrl 17 block diagram changed the resource name. 16-bit i/o timer 16-bit free-run timer 32 interrupt factors, interrupt vectors, interrupt control register changed the interrupt cause name of the interrupt vector number #19. input/output timer 16-bit free-run timer 39 electrical characteristics 4. ac characteristics changed the "(1) clock timing". added the limitation when pll is used for the clock frequency. 44 changed the symbol t rhlh of (5) bus timing (read). rd rd 49 electrical characteristics 4. ac characteristics (9) uart0/1, serial i/o timing changed the value of serial clock cycle time. min : 8t cp 4t cp mb90440g series 62 ds07-13716-3e memo mb90440g series ds07-13716-3e 63 memo mb90440g series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu. com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectroni cs pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further inform ation please cont act each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the de vice with respect to use based on such information. when you develop equipment incor porating the device based on such inform ation, you must assume any res ponsibility arising out of su ch use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fa tal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead direct ly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight contro l, air traffic control, mass tr ansport control, medical life s upport system, missile launch con trol in weapon system), or (2) for use requiring extrem ely high reliability (i.e., submersibl e repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited: business & media promotion dept. |
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